1. Field of the Invention
The invention pertains to integrated circuits with memory, more particularly, to electrically erasable programmable memories, and notably to their erasure.
An electrically erasable and programmable memory (or EEPROM) is a read-only memory, namely a memory that preserves the items of memory stored therein, even when power is no longer supplied. Such a memory also has the particular feature of being erasable, byte by byte, for example, by means of an electrical pulse. The terms "programming" and "erasure" will be used hereafter in accordance with a convention commonly used for EEPROM products.
As explained below, the electrical programming and erasure is obtained by the extraction of charges from the substrate and their storage beneath a floating gate, and the return of these same charges to the substrate by tunnel effect. However, explained in greater detail, this phenomenon is not an everlasting one: after a certain number of programming or writing and erasing cycles, the cell, namely the basic memory element, gradually deteriorates so it no longer properly carries out the writing or erasing functions.
2. Description of the Prior Art
Up till now, in the applications using EEPROM components subjected to frequent updating operations, faults have been observed after an unknown and variable number of uses. When this type of problem occurs, during use of the EEPROM, there may be major problems with the larger device or system in which the EEPROM is used. To check the exactness of the items of information modified after a writing or erasing cycle, it becomes necessary for the application to include a systematic re-reading operation. Should the re-reading operation, after a writing operation, highlight an anomaly, the programming or writing is repeated or rewritten, and this rewriting is done until the re-reading is accurate. In a known procedure, the pieces of information to be recorded are rewritten a certain number of times. This number depends on the technology of the memory. There is a similar problem for the erasure: the erasure may have to be reiterated. The only thing is that, for the erasure, the number of operations changes over time or with the use of the memory.
To obtain conditions of operation that are always appropriate, it might be possible to envisage counting the number of erasure/reading cycles in a counter and carrying out a verification in declaring the EEPROM to be out of operation once this number goes beyond a pre-determined threshold which, in this case, would have to be low enough to prevent any risk of malfunctioning. However, since these memories are generally found to be in contexts where they are not supplied with power, example (in chip cards, portable machines, configuration fall-back systems etc.) this counter would have to be housed in the EEPROM memory itself, which would then be overtaxed in comparison to what is being counted. This counter, made by means of the same technology as the memory cells, is naturally subject to the same failures.
Furthermore, it is unfortunately impossible to determine in advance the critical number of cycles beyond which an EEPROM memory is defective: this number varies from one fabrication technology to another, from one product to another within one and the same fabrication technology, from one component to another within one product according to parameters that may be known but often cannot be controlled, such as the temperature, time or programming voltage, etc.
However, experience has shown that the behavior of the cells subsequent to faults is always substantially the same.